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Rev 0; 2/08
I2C Gamma and VCOM Buffer with EEPROM
General Description
The DS3510 is a programmable gamma and VCOM voltage generator which supports both real-time updating as well as multibyte storage of gamma/VCOM data in onchip EEPROM memory. An independent 8-bit DAC, two 8-bit data registers, and 4 bytes of EEPROM memory are provided for each individually addressable gamma or VCOM channel. High-performance buffer amplifiers are integrated on-chip, providing rail-to-rail, low-power (400A/gamma channel) operation. The VCOM channel features a high-current drive (> 250mA peak) and a fastsettling buffer amplifier optimized to drive the VCOM node of a wide range of TFT-LCD panels. Programming occurs through an I2C-compatible serial interface. Interface performance and flexibility are enhanced by a pair of independently loaded data registers per channel, as well as support for I2C speeds up to 400kHz. The multitable EEPROM memory enables a rich variety of display system enhancements, including support for temperature or light-level-dependent gamma tables, enabling of factory or field automated display adjustment, and support for backlight dimming algorithms to reduce system power. Upon power-up and depending on mode, DAC data is selected from EEPROM by the S0/S1 pads or from a fixed memory address. o 8-Bit Gamma Buffers, 10 Channels o 8-Bit VCOM Buffer, 1 Channel o 4 EEPROM Bytes per Channel o Low-Power 400A/ch Gamma Buffers o I2C-Compatible Serial Interface o Flexible Control from I2C or Pins o 9.0V to 15.0V Analog Supply o 2.7V to 5.5V Digital Supply o 48-Pin Package (TQFN 7mm x 7mm)
Features
DS3510
Ordering Information
PART DS3510T+ DS3510T+T&R TEMP RANGE -45C to +95C -45C to +95C PIN-PACKAGE 48 TQFN-EP* 48 TQFN-EP*
+Denotes a lead-free package. T&R = Tape and reel. *EP = Exposed pad.
Applications
TFT-LCD Gamma and VCOM Buffer Adaptive Gamma and VCOM Adjustment (RealTime by I2C, Select EEPROM Through I2C or S0/S1 Pads) Industrial Process Control
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
Gamma or VCOM Channel Functional Diagram
SDA, SCL A0 I2C INTERFACE
LATCH A MUX LATCH B
8-BIT DAC VOUT
IN S1/ S0 LOGIC EEPROM ADDRESS
OUT
LD
________________________________________________________________ Maxim Integrated Products
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I2C Gamma and VCOM Buffer with EEPROM DS3510
ABSOLUTE MAXIMUM RATINGS
Voltage on VDD Relative to GND ............................-0.5V to +16V Voltage on VRL, VRH, GHH, GHM, GLM, GLL Relative to GND........-0.5V to (VDD + 0.5V), not to exceed 16V Voltage on VCC Relative to GND ..............................-0.5V to +6V Voltage on SDA, SCL, A0, LD, S0, S1 Relative to GND ....-0.5V to (VCC + 0.5V), not to exceed 6V Junction Temperature ......................................................+125C Operating Temperature Range ...........................-45C to +95C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...............Refer to IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -45C to +95C.)
PARAMETER Digital Supply Voltage Analog Supply Voltage VRH, VRL Voltage GHH, GHM, GLM, GLL Voltage Input Logic 1 (SCL, SDA, A0, S0, S1, LD) Input Logic 0 (SCL, SDA, A0, S0, S1, LD) VCOM Load Capacitor VCAP Compensation Capacitor SYMBOL VCC VDD VVCOM VGM1-10 VIH VIL CD CCOMP (Note 1) (Note 1) Applies to VCOM output Applies to GM1-GM10 CONDITIONS MIN +2.7 +9.0 +2.0 GND + 0.2 0.7 x VCC -0.3 1 0.1 TYP MAX +5.5 +15.0 VDD - 2.0 VDD - 0.2 VCC + 0.3 0.3 x VCC UNITS V V V V V V F F
INPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER Input Leakage (SDA, SCL, S0, S1, LD) Input Leakage (A0) VDD Supply Current VCC Supply Current, Nonvolatile Read or Write VCC Standby Supply Current VDD Standby Supply Current I/O Capacitance (SDA, SCL, A0) End-to-End Resistance (VRH to VRL) SYMBOL IL IL:A0 IDD ICC ICCQ IDDQ CI/O RTOTAL (Notes 2, 3) (Note 4) (Note 5) (Note 6) (Note 7) 6.7 0.2 1.8 2 5 16 CONDITIONS MIN -1 TYP MAX +1 2 15.0 1.0 10.0 4 10 UNITS A mA mA mA A mA pF k
2
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I2C Gamma and VCOM Buffer with EEPROM
INPUT ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER RTOTAL Tolerance Input Resistance (GHH, GHM, GLM, GLL) Input Resistance Tolerance TA = +25C -20 SYMBOL TA = +25C CONDITIONS MIN -20 75 +20 TYP MAX +20 UNITS % k %
DS3510
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, VRL = GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = GHH = +14.8V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER VCOM/GM1-10 DAC resolution Integral Nonlinearity Error Differential Nonlinearity Error Output Voltage Range (VCOM) Output Voltage Range (GM1-10) Output Accuracy (VCOM, GM1-10) Voltage Gain (GM1-10) Load Regulation (VCOM, GM1-10) Short-Circuit Current (VCOM) S0/S1 to LD Setup Time S0/S1 to LD Hold Time VCOM Settling Time from LD Low to High (S0/S1 Meet t SU) GM1-10 Settling Time from LD Low to High S0, S1 to VCOM or GM1-10 Output 10% Settled t SU tHD t SET-V t SET-G t SEL To VDD or GND Figure 1 or 2 Figure 1 or 2 Settling to 0.1% (see Figure 1) (Notes 3, 11) 4 tau settled with ILOAD= 20mA (see Figure 2) (Notes 3, 11, 12) 10% settling (see Figure 3), LD = VCC (asynchronous) (Note 12) 250 200 200 2 6.7 450 TA = +25C (Note 10) VCOM Gamma INL DNL (Note 8) VCOM Gamma VCOM/gamma (Note 9) SYMBOL CONDITIONS MIN 8 -0.75 -0.4 -0.3 2.0 0.2 -25 -50 0.995 0.5 +0.75 LSB +0.4 +0.3 VDD - 2.0 VDD - 0.2 +25 mV +50 V/V mV/mA mA ns ns s s ns LSB V V TYP MAX UNITS Bits
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I2C Gamma and VCOM Buffer with EEPROM DS3510
I2C ELECTRICAL CHARACTERISTICS (See Figure 4)
(VCC = +2.7V to +5.5V, TA = -45C to +95C, timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time Pulse-Width Suppression Time at SDA and SCL Inputs A0 Setup Time A0 Hold Time SDA and SCL Input Buffer Hysteresis Low-Level Output Voltage (SDA) SCL Falling Edge to SDA Output Data Valid Output Data Hold VOL tAA tDH 4mA sink current SCL falling through 0.3VCC to SDA exit 0.3VCC ~0.7VCC window SCL falling through 0.3VCC until SDA in 0.3VCC ~0.7VCC window 0 SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tHD:DAT t SU:DAT t SU:STA tR tF t SU:STO CB tW t IN t SU:A tHD:A (Note 14) (Note 15) (Note 16) Before START After STOP 0.6 0.6 0.05 x VCC 0.4 900 (Note 14) (Note 14) (Note 13) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 50 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms ns s s V V ns ns
4
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I2C Gamma and VCOM Buffer with EEPROM
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V.)
PARAMETER EEPROM Write Cycles EEPROM Write Cycles SYMBOL TA = +70C TA = +25C CONDITIONS MIN 50,000 200,000 MAX UNITS Writes Writes
DS3510
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Note 9:
Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16:
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. IDD supply current is specified with VDD = 15.0V and no load on VCOM or GM1-10 outputs. Specified with the VCOM and gamma bias currents set to 100%. ICC is specified with the following conditions: SCL = 400kHz, SDA = VCC = 5.5V, and VCOM and GM1-10 floating. ICCQ is specified with the following conditions: SCL = SDA = VCC = 5.5V, and VCOM and GM1-10 floating. IDDQ is specified with the following conditions: SCL = SDA = VCC = 5.5V and VCOM and GM1-10 floating. Guaranteed by design. Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. INL = [V(RW)i - (V(RW)0]/LSB(measured) - i, for i = 0...255. Differential nonlinearity is the deviation of the step size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i]/LSB(measured) - 1, for i = 0...254. Tested at VRL = VRH = 6.5V/7.5V/8.5V, GLL = GLM = 0.5V/6.5V/8.5V/14.5V, GHM = GHH = 0.5V/6.5V/8.5V/14.5V. EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected. Rising transition from 5V to 10V; falling transition from 10V to 5V. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing. CB--total capacitance of one bus line in picofarads. EEPROM write time begins after a STOP condition occurs. Pulses narrower than max are suppressed.
S0/S1
VIH VIL tHD tSU tSET-V 2 VIH VCOM 100nF
LD VIL
0.1% SETTLED
VCOM
Figure 1. VCOM Settling Timing Diagram
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I2C Gamma and VCOM Buffer with EEPROM DS3510
S0/S1 VIH VIL tHD tSU tSET-G GM1-GM10 VIH LD VIL ILOAD 100pF
4 TAU SETTLED
GM1-10
Figure 2. GM1-10 Settling Timing Diagram
S0/S1 (LD = VCC)
VIH VIL GM1-GM10 tSEL OUTPUT 10% SETTLED 100pF
GM1-GM10
Figure 3. Input Pin to Output Change Timing Diagram
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 4. I2C Timing Diagram 6 _______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ICC vs. VCC
DS3510 toc01
DS3510
IDD vs. VDD
DS3510 toc02
ICC vs. TEMPERATURE
DS3510 toc03
180 160 +95C 140 +25C
7.0 +95C 6.5 +25C 6.0 IDD (mA) 5.5 5.0 4.5 4.0
180 160 5.5V 140 ICC (A)
ICC (A)
120 100 80 60 2.7 3.2 3.7 4.2 VCC (V)
-40C
-40C
120 3.6V 100 80 60 2.7V
4.7
5.2
9
10
11
12 VDD (V)
13
14
15
-45
0
45
90
TEMPERATURE (C)
IDD vs. VDD
DS3510 toc04
IDD vs. BIAS CURRENT SETTING
VCC = 4V, VDD = 15V 8 7 IDD (mA)
DS3510 toc05
VCOM INL vs. SETTING
0.65 0.45 VCOM INL (LSB) 0.25 0.05 -0.15 -0.35
DS3510 toc06
7.0 6.5 6.0 IDD (mA) 5.5 -40C 5.0 4.5 4.0 -45 0 VDD (V) 45 90 +25C +95C
9
6 5 4 3 0 1 2 3 BIAS CURRENT SETTING (DEC)
-0.55 -0.75 0 50 100 150 200 250 VCOM SETTING (DEC)
VCOM DNL vs. SETTING
DS3510 toc07
GM1-GM10 INL vs. SETTING
DS3510 toc08
GM1-GM10 DHL vs. SETTING
DS3510 toc09
0.3 0.2 VCOM DNL (LSB) 0.1 0 -0.1 -0.2
0.4 0.3 GM1-GM10 INL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3
0.3 0.2 GM1-GM10 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3
-0.3 0 50 100 150 200 250 VCOM SETTING (DEC)
-0.4 0 50 100 150 200 250 GM1-GM10 SETTING (DEC)
0
50
100
150
200
250
GM1-GM10 SETTING (DEC)
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I2C Gamma and VCOM Buffer with EEPROM DS3510
Pin Description
NAME VDD GND PIN 1, 19, 20, 24 2, 38, 40, 42, 43 TYPE Power Power Analog Supply (9.0V to 15.5V) Ground Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch). When LD is high, the input to Latch B data flows through to the output and updates the DACs asynchronously. Select Inputs. When Control register [1,0] = 00, S0 and S1 pins are used to select DAC input data from EEPROM. I2C Serial Clock Input I2C Serial Data Input/Output Address Input. This pin determines I2C slave address of the DS3510. Digital Supply (2.7V to 5.5V) VCOM Reference Inputs. High-voltage reference for VCOM DAC. FUNCTION
LD S1 S0 SCL SDA A0 VCC VRH, VRL
3 4
Input
Input 5 6 7 8 9 10, 11 12-17, 23, 36, 37, 44-48 18 21, 22 25-29 30 31-35 41, 39 EP Input Input/Output Input Power Reference Input
N.C. VCAP GLL, GLM GM1-GM5 VCOM GM6-GM10 GHM, GHH GND
-- Input Reference Input Output Output Output Reference Input --
No Connection Compensation Capacitor Input. Connect VCAP to GND through a 0.1F capacitor. References for Low-Voltage Gamma DAC Low-Voltage Gamma Analog Outputs VCOM Analog Output. This output requires a 1F capacitor to GND. High-Voltage Gamma Analog Outputs References for High-Voltage Gamma DAC Ground. Exposed pad. Connect to GND.
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I2C Gamma and VCOM Buffer with EEPROM
Block Diagram
GHH BANKS GM10 BANK A GM10 BANK B GM10 BANK C GM10 BANK D S0/S1 PINS S0/S1 BITS I2C COMP 0 LATCH A GHH MUX 0 8 BITS LATCH B 1 LD GHM MODE0 BIT MODE1 BIT 8-BIT DAC GM10 GHH
DS3510
DS3510
1
BANKS GM6 BANK A GM6 BANK B GM6 BANK C GM6 BANK D S0/S1 PINS S0/S1 BITS I2C COMP 0
GHH MUX 0 8 BITS LATCH B 1 LATCH A LD GHM 8-BIT DAC GM6
1
SDA SCL A0
I2C INTERFACE
I2C
MODE0 BIT
MODE1 BIT GHM GHM
MODE0 BIT (CR.0) S0 S1 LD LOGIC AND CONTROL MODE1 BIT (CR.1) S0/S1 PINS S0/S1 BITS (SOFT S0/S1) LD I2C COMP
BANKS VCOM BANK A VCOM BANK B VCOM BANK C VCOM BANK D S0/S1 PINS S0/S1 BITS 0
VRH MUX 0 8 BITS LATCH B 1 LATCH A LD VRL MODE0 BIT MODE1 BIT GLM GLM 8-BIT DAC VCOM
1
VCAP
COMPENSATION
COMP
BANKS GM5 BANK A GM5 BANK B GM5 BANK C GM5 BANK D S0/S1 PINS S0/S1 BITS 0
GLM MUX 0 8 BITS LATCH B 1 LATCH A LD GLL 8-BIT DAC GM5
1
VDD VDD VCC VCC BANKS GM1 BANK A GM1 BANK B GM1 BANK C GM1 BANK D S0/S1 PINS S0/S1 BITS I2C COMP 0 LATCH A I2C COMP MODE0 BIT MODE1 BIT
GLM MUX 0 8 BITS LATCH B 1 LD GLL MODE0 BIT MODE1 BIT GLL GLL 8-BIT DAC GM1
GND
1
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I2C Gamma and VCOM Buffer with EEPROM DS3510
Detailed Description
The DS3510 operates in one of three modes which determine how the VCOM and gamma DACs are controlled/updated. The first two modes allow "banked" control of the 10 gamma channels and 1 VCOM channel. Depending on the mode, one of four banks (in EEPROM) can be selected using either the S0/S1 pins or using the SOFT S0/S1 bits in the Soft S0/S1 register. Once a bank is selected, the LD pin can then be used to simultaneously update each channel's DAC output. The third and final mode is not banked. It allows I2C control of each channel's Latch A register which is SRAM (volatile), allowing quick and unlimited updates. In this mode, the LD pin can also be used to simultaneously update each channel's DAC output. A detailed description of the three modes as well as additional features of the DS3510 follows. changes in the state of S0/S1 to meet the tSEL specification. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by S0/S1. A high-to-low transition on LD latches the selected DAC data into Latch B.
Table 2. DS3510 Bank Selection Table
S1 0 0 1 1 S0 0 1 0 1 VCOM CHANNEL VCOM Bank A VCOM Bank B VCOM Bank C VCOM Bank D GAMMA CHANNELS GM1-10 Bank A GM1-10 Bank B GM1-10 Bank C GM1-10 Bank D
Mode Selection
The DS3510 mode of operation is determined by 2 bits located in the Control register (60h), which is nonvolatile (NV) (EEPROM). In particular, the mode is determined by the MODE0 bit (CR.0) and the MODE1 bit (CR.1). Table 1 illustrates how the 2 control bits are used to select the operating mode. When shipped from the factory, the DS3510 is programmed with both MODE bits set to zero.
SOFT S0/S1 (Bit) Controlled Bank Updating Mode
This mode also features "banked" operation with the only difference being how the desired bank is selected. In particular, the bank is selected using the SOFT S0 (bit 0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1 register (50h). The S0 and S1 pins are ignored in this mode. Table 2 illustrates the relationship between the bit settings and the selected bank. For example, if both bits, S0 and S1, are written to zero, then the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of the LD pin. When LD is high, Latch B functions as a flowthrough latch, so the amplifier will respond asynchronously to changes in the state of the S0/S1 bits. These are changed by an I2C write. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by the S0/S1 bits. A highto-low transition on LD latches the selected DAC data into Latch B. Since the Soft S0/S1 register is SRAM, subsequent power-ups result in the SOFT S0 and SOFT S1 bits being cleared to 0 and, hence, powering up to Bank A.
Table 1. DS3510 Operating Modes
MODE1 BIT (CR.1) 0 0 1 MODE0 BIT (CR.0) 0 1 X MODE S0/S1 Pin-Controlled Bank Updating (Factory Default) S0/S1 Bit-Controlled Bank Updating I2C Individual Channel Control
S0/S1 Pin-Controlled Bank Updating Mode
As shown in the block diagram, each channel contains 4 bytes of EEPROM, which are used to implement the "banking" functionality. Each "bank" contains unique DAC settings for each channel. When the DS3510 is configured in this operating mode, the desired bank is selected using the S0 and S1 pins as shown in Table 2 where 0 is ground and 1 is VCC. For example, if S0 and S1 are both connected to ground, then the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of LD pin. When LD is high, Latch B functions as a flow-through latch, so the amplifier will respond asynchronously to
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I2C Individual Channel Control Mode
In this mode the I2C master writes directly to individual channel Latch A registers to update a single DAC (i.e., not banked). The Latch A registers are SRAM and not EEPROM. This allows an unlimited number of write cycles as well as quicker write times since t W only applies to EEPROM writes. As shown in the Memory Map, the Latch A registers for each channel are accessed through memory addresses 00-0Ah. Then,
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I2C Gamma and VCOM Buffer with EEPROM
Table 3. DAC Voltage/Data Relationship for Selected Codes
SETTING (HEX) 00h 01h 02h 03h 0Fh 3Fh 7Fh FDh FEh FFh VCOM OUTPUT VOLTAGE VRL VRL + (1/255) x (VRH - VRL) VRL + (2/255) x (VRH - VRL) VRL + (3/255) x (VRH - VRL) VRL + (15/255) x (VRH - VRL) VRL + (63/255) x (VRH - VRL) VRL + (127/255) x (VRH - VRL) VRL + (253/255) x (VRH - VRL) VRL + (254/255) x (VRH - VRL) VRH GM1-GM5 OUTPUT VOLTAGE GLL GLL + (1/256) x (GLM - GLL) GLL + (2/256) x (GLM - GLL) GLL + (3/256) x (GLM - GLL) GLL + (15/256) x (GLM - GLL) GLL + (63/256) x (GLM - GLL) GLL + (127/256) x (GLM - GLL) GLL + (253/256) x (GLM - GLL) GLL + (254/256) x (GLM - GLL) GLL + (255/256) x (GLM - GLL) GM6-GM10 OUTPUT VOLTAGE GHM + (255/256) x (GHH - GHM) GHM + (254/256) x (GHH - GHM) GHM + (253/256) x (GHH - GHM) GHM + (252/256) x (GHH - GHM) GHM + (240/256) x (GHH - GHM) GHM + (192/256) x (GHH - GHM) GHM + (128/256) x (GHH - GHM) GHM + (2/256) x (GHH - GHM) GHM + (1/256) x (GHH - GHM) GHM
DS3510
like the other modes, the LD pin determines when the DACs get updated. If the LD signal is high, Latch B is flow-through and the DAC is updated immediately. If LD is low, Latch B will be loaded from Latch A after a low-to-high transition on the LD pin. This latter method allows the timing of the DAC update to be controlled by an external signal pulse.
impedance state. Current drawn from the VDD supply in this state is specified as IDDQ. The DS3510 continues to respond to I2C commands, and thus draws some current from VCC when I2C activity is occurring. When the I2C interface is inactive, current drawn from the VCC supply is specified as ICCQ.
VCOM/Gamma Channel Outputs
As illustrated in the Block Diagram, the V COM and gamma channel outputs are equivalent to an 8-bit digital potentiometer (DAC) with a buffered output. The VCOM channel's digital potentiometer is comprised of 255 equal resistive elements. The relationship between output voltage and DAC setting is illustrated in Table 3. Unlike the gamma channels, the V COM channel is capable of outputting a range of voltages including both references (VRH and VRL). Each of the gamma channel digital potentiometers, on the other hand, are comprised of 256 equal resistive elements. The extra resistive element prohibits one of the rails from being reached. In particular, gamma channel outputs GM1-GM5 can span from (and including) GLL to 1 LSB away from GLM. Likewise, gamma channel outputs GM6-GM10 span from (and including) GHM to 1 LSB away from GHH. The relationship between output voltage and DAC setting for the gamma channels is also illustrated in Table 3.
Thermal Shutdown
As a safety feature, the DS3510 goes into a thermal shutdown state if the junction temperature ever reaches or exceeds +150C. In this state, the VCOM buffer is disabled (output goes high impedance) until the junction temperature falls below +150C.
Slave Address Byte and Address Pin
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 5). The DS3510's slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same I2C bus. Connecting A0 to GND results in a 0 in the corresponding bit position in the slave address. Conversely, connecting A0 to VCC results in a 1 in the corresponding bit position. For example, the DS3510's slave address byte is C0h when A0 is grounded. I2C communication is described in detail in the I2C Serial Interface Description section.
MSB LSB 1 0 0 0 0 A0 R/W
Standby Mode
Standby mode (not to be confused with the three DS3510 operating modes) can be used to minimize current consumption. Standby mode is entered by setting the standby bit, which is the LSB of register 51h. The VCOM and gamma outputs are placed in a high-
1
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
Figure 5. DS3510 Slave Address Byte
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I2C Gamma and VCOM Buffer with EEPROM DS3510
Memory Organization
Memory Description
The list of registers/memory contained in the DS3510 is shown in the Memory Map. Also shown for each of the registers is the memory type and accessibility, as well as the power-up default values for volatile locations and
ADDR (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B-0F 10-13 14-17 18-1B 1C-1F 20-23 24-27 28-2B 2C-2F 30-33 34-37 38-3B 3C-4F 50 51 52-56 57 58-5F 60 61-FF
factory-programmed defaults for the NV locations. Detailed register descriptions for the registers shown in bold follow in the Detailed Register Descriptions section. Furthermore, additional information regarding reading and writing the memory is located in the I2C Serial Interface Description section.
Memory Map
NAME VCOM Latch A GM1 Latch A GM2 Latch A GM3 Latch A GM4 Latch A GM5 Latch A GM6 Latch A GM7 Latch A GM8 Latch A GM9 Latch A GM10 Latch A Reserved VCOM Bank A-D GM1 Bank A-D GM2 Bank A-D GM3 Bank A-D GM4 Bank A-D GM5 Bank A-D GM6 Bank A-D GM7 Bank A-D GM8 Bank A-D GM9 Bank A-D GM10 Bank A-D Reserved Soft S0/S1 Standby Reserved Status Reserved Control Register (CR) Reserved DESCRIPTION Data for I2C Control of VCOM Data for I2C Control of GM1 Data for I2C Control of GM2 Data for I2C Control of GM3 Data for I2C Control of GM4 Data for I2C Control of GM5 Data for I2C Control of GM6 Data for I2C Control of GM7 Data for I2C Control of GM8 Data for I2C Control of GM9 Data for I2C Control of GM10 Reserved VCOM EEPROM Data (4 Bytes) GM1 EEPROM Data (4 Bytes) GM2 EEPROM Data (4 Bytes) GM3 EEPROM Data (4 Bytes) GM4 EEPROM Data (4 Bytes) GM5 EEPROM Data (4 Bytes) GM6 EEPROM Data (4 Bytes) GM7 EEPROM Data (4 Bytes) GM8 EEPROM Data (4 Bytes) GM9 EEPROM Data (4 Bytes) GM10 EEPROM Data (4 Bytes) Reserved Software Bank Select Bits Standby (xxxxxxx, Standby) Reserved Status Bits (LD, xxxxx, S1, S0) Reserved Control Register Reserved MEMORY TYPE Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile -- NV NV NV NV NV NV NV NV NV NV NV -- Volatile Volatile -- Status -- NV -- I2C ACCESS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W -- R -- R/W -- DEFAULT (HEX) 00 00 00 00 00 00 00 00 00 00 00 -- 80 80 80 80 80 80 80 80 80 80 80 -- 00 00 -- N/A -- 10 --
12
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I2C Gamma and VCOM Buffer with EEPROM
Detailed Register Descriptions
SOFT S0/S1 50h: SOFT S1/S0 Bits FACTORY DEFAULT MEMORY TYPE 00h Volatile
DS3510
50h
x bit7
x
x
x
x
x
SOFT S1
SOFT S0 bit0
bit7:2
Reserved These bits are used when in SOFT S0/S1 (bit) Controlled Bank Updating Mode (MODE1 = 0, MODE0 = 1) SOFT S1, SOFT S0: 00 = Selects VCOM and GM1-GM10 Bank A 01 = Selects VCOM and GM1-GM10 Bank B 10 = Selects VCOM and GM1-GM10 Bank C 11 = Selects VCOM and GM1-GM10 Bank D
bit1, bit0
STANDBY 51h: Standby Mode Enable FACTORY DEFAULT MEMORY TYPE 00h Volatile
51h
x bit7
x
x
x
x
x
x
Standby bit0
bit7:1
Reserved Standby: 0 = Standby Mode Disabled 1 = Standby Mode Enabled
bit0
STATUS 57h: Real-Time Indicator of Logic State on LD, S1, and S0 Pins FACTORY DEFAULT MEMORY TYPE -- Read Only
57h
LD bit7
x
x
x
x
x
S1
S0 bit0
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13
I2C Gamma and VCOM Buffer with EEPROM DS3510
CONTROL REGISTER 60h: Control Register (CR) FACTORY DEFAULT MEMORY TYPE 10h NV
60h
x bit7
x
BIAS1
BIAS0
x
x
MODE1
MODE0 bit0
bit7:6
Reserved VCOM and Gamma Bias Current Control Bits: 00 = 150% 01 = 100% (default) 10 = 80% 11 = 60% Reserved DS3510 Mode: 00 = S0/S1 Pins are Used to Select the Desired Bank (A-D) (Default) 01 = Soft S0/S1 (Bits) Are Used to Select the Desired Bank (A-D) 1X = Latch A Is Used to Control the DACs
bit5:4
bits3:2
bits1:0
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I 2C data transfers. (See Figure 4 and I 2C Electrical Characteristics for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a
specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data.
14
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I2C Gamma and VCOM Buffer with EEPROM
Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS3510's slave address is determined by the state of the A0 address pin as shown in Figure 5. An address pin connected to GND results in a 0 in the corresponding bit position in the slave address. Conversely, an address pin connected to VCC results in a 1 in the corresponding bit position. When the R/W bit is 0 (such as in C0h), the master is indicating it will write data to the slave. If R/W is set to a 1, (C1h in this case), the master is indicating it wants to read from the slave. If an incorrect (non-matching) slave address is written, the DS3510 will assume the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory address: During an I2C write operation to the DS3510, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgment during all byte write operations. When writing to the DS3510 (and if LD = 1), the DAC will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) will be written following the STOP condition at the end of the write command. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3510 is capable of writing 1 to 8 bytes (1 page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3510 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3510, which allows communication to continue as soon as the DS3510 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device.
DS3510
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15
I2C Gamma and VCOM Buffer with EEPROM DS3510
TYPICAL I2C WRITE TRANSACTION MSB START 1 1 0 0 0 0 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND) C0h A) SINGLE-BYTE WRITE -WRITE LATCH A GM8 TO 00h 08h OOh SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK C1h REPEATED START 1 1 0 0 0 0 0 1 SLAVE ACK STOP
START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 ACK C0h 02h
DATA I/O STATUS MASTER NACK STOP
B) SINGLE-BYTE READ -READ LATCH A GM2
START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 0 0 1 0 SLAVE ACK ACK
C0h C) SINGLE-BYTE WRITE -ENTER STANDBY MODE START 1 1 0 0 0 0 0 0 SLAVE ACK
51h 01010 001 SLAVE ACK
01h 0000 0 0 0 1 SLAVE ACK STOP
C0h D) TWO-BYTE WRITE - WRITE 10h AND 11h TO 80h START 1 1 0 0 0 0 0 0 SLAVE ACK
10h 00010 000 SLAVE ACK
80h 1000 0 0 0 0 SLAVE ACK
80h 1000 0 0 0 0 SLAVE ACK STOP
C0h E) TWO-BYTE READ - READ 10h AND 11h START 1 1 0 0 0 0 0 0 SLAVE ACK
10h 00010 000 SLAVE ACK REPEATED START
C1h 1100 0 0 0 1 SLAVE ACK
DATA MASTER ACK
DATA MASTER NACK STOP
Figure 6. I2C Communication Examples
EEPROM write cycles: The DS3510's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room temperature. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location.
Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Recall that the master must NACK the last byte to inform the slave that no additional bytes will be read. See Figure 6 for I2C communication examples. Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it must NACK to indicate the end of the transfer and generates a STOP condition.
16
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I2C Gamma and VCOM Buffer with EEPROM
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3510, decouple all the power-supply pins (VCC and VDD) with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I 2 C Electrical Characteristics are within specification. A typical value for the pullup resistors is 4.7k.
DS3510
Typical Operating Circuit
15V 5V VDD VCC GHH GHM GLM GLL GM1 GM2 GM3 GM4 GM5 14.8V 8V 7V 0.2V 8 SOURCE DRIVER
I2C MASTER
SCL SDA A0 GND VRH
DS3510
GM6 GM7 GM8 GM9 GM10 VCOM 8
LCD
VRL
7.5V
2V
Pin Configuration
GMH GND GND GND GHH GND N.C. N.C. N.C. N.C. N.C. N.C.
Package Information
(For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE PACKAGE CODE T4877+6 DOCUMENT NO. 21-0144
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 VDD GND LD S1 S0 SCL SDA A0 VCC VRH VRL N.C. 1 2 3 4 5 6 7 8 9 10 *EP 11 12 13 14 15 16 17 18 19 20 21 22 23 24 N.C. N.C. N.C. N.C. N.C. GLL GLM N.C. VDD VDD VCAP VDD 26 GM2 25 GM1 36 35 34 33 32 31 N.C. GM10 GM9 GM8 GM7 GM6
48 TQFN-EP
DS3510
30 VCOM 29 28 GM5 GM4
27 GM3
TQFN (7mm x 7mm x 0.8mm)
*EXPOSED PAD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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